1. Field of the Invention
This invention relates to delay-locked loops in general, and more particularly, to delay-locked loops utilizing digital differential controlled delay elements and pulse skew correcting detectors.
2. Description of the Prior Art
Traditional phase-locked loop (PLL) design involves using a voltage-controlled oscillator (VCO) to provide a local signal which is phase-locked onto an input signal. Implementing the VCO in an integrated circuit, as known in the prior art, typically uses a frequency determining network external to the IC to establish the nominal operating frequency of the VCO. Exemplary frequency determining networks are a resistor-capacitor or an inductor-capacitor combination. Although external frequency determining networks are advantageous for general purpose PLL designs, it is desirable to have fully integrated PLL designs, such as in microprocessors and data communications applications where space and cost are primary concerns. In microprocessor applications, many clock phases are needed which are precisely spaced from one another and are precisely "slaved" to the system clock.
One approach to providing a fully integrated PLL design is disclosed in "Design of PLL-Based Clock Generation Circuits" by D-K Jeong, et al., IEEE Journal of Solid-State Circuits, Vol. SC-22, Apr. 1987, pp. 255-261. In particular, the VCO portion is implemented using a ring oscillator (FIG. 4, p. 257), the frequency thereof being determined by varying the delay provided by multiple series-connected delay cells (or elements) making up the ring oscillator. In FIG. 3(c), the basic delay cell is shown having an inverter, consisting of two transistors with common drain terminals and common gate terminals, powered by two current sources, formed by the remaining transistors, with the output of the inverter buffered by a Schmitt trigger and a buffer. The delay provided by the delay cell is substantially determined by the current supplied to the inverter by the current sources.
The main drawback of this technique is the variation of the characteristics of the inverter and current sources caused by processing variations in the manufacture of the IC. When the processing is "fast", for a given desired delay to provide the desired oscillation frequency (or when long delays are desired regardless of the processing variations), the current level supplied to the inverter must be severely restricted. At these lower currents, the output signal is restricted in amplitude, and the inverter generates large amounts of thermal noise and is susceptible to power supply noise. The combination of these problems causes unreliable delay times which, in turn, cause the VCO based on these delay elements to have unstable, uncontrollable characteristics.